DocumentCode
2107335
Title
Equivalence Checking for Intelligent Circuits
Author
Fan, De-Hui ; Ma, Guang-Sheng
Author_Institution
Coll. of Comput. Sci. & Technol., Harbin Eng. Univ., Harbin
fYear
2008
fDate
21-22 Dec. 2008
Firstpage
785
Lastpage
787
Abstract
Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for checking. comparing the model WLDDs, the experiments show that the WGL is more efficient.
Keywords
circuit CAD; graph theory; polynomials; Weighted Generalized List; equivalence checking; intelligent circuits design; Application software; Boolean functions; Circuit simulation; Circuit synthesis; Computer science; Data structures; Delay effects; Educational institutions; Information technology; Polynomials; WGL; equivalence checking; formal verification;
fLanguage
English
Publisher
ieee
Conference_Titel
Intelligent Information Technology Application Workshops, 2008. IITAW '08. International Symposium on
Conference_Location
Shanghai
Print_ISBN
978-0-7695-3505-0
Type
conf
DOI
10.1109/IITA.Workshops.2008.188
Filename
4732054
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