DocumentCode
2107339
Title
A 2/spl times/ load/store pipe for a low-power 1GHz embedded processor
Author
Zongjian Chen ; Murrray, D. ; Nishinnoto, S. ; Pearce, M. ; Oyker, M. ; Rodriguez, D. ; Rogenmoser, R. ; Suh, D. ; Supnet, E. ; Yiu, G.
Author_Institution
Broadcom, Santa Clara, CA, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
340
Abstract
The load/store pipe in an embedded processor is clocked at 2/spl times/ the processor clock frequency. It sustains two load or store operations per core clock cycle with zero load-to-use issue latency. The design is implemented in 0.13/spl mu/m 7M CMOS process and dissipates between 650 and 1090mW for core clock frequencies between 600MHz and 1GHz.
Keywords
CMOS digital integrated circuits; low-power electronics; microprocessor chips; pipeline processing; 0.13 micron; 600 MHz to 1 GHz; 650 to 1090 mW; CMOS; core clock frequencies; embedded processor; load-to-use issue latency; load/store pipe; low-power IC; Buffer storage; Circuits; Clocks; Decoding; Delay; Frequency; Pipelines; Registers; Road transportation; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234325
Filename
1234325
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