Title :
A clock skew absorbing flip-flop
Author :
Nedovic, N. ; Oklobdzija, V.G. ; Walker, W.W.
Author_Institution :
Fujitsu Labs. of America, Sunnyvale, CA, USA
Abstract :
A 0.11/spl mu/m 1.2V CMOS flip-flop absorbs up to 50ps of clock skew. Measured results confirm 27% delay and 33% energy-delay product improvement over previously reported flip-flops, regardless of clock skew.
Keywords :
CMOS logic circuits; flip-flops; sequential circuits; 0.11 micron; 1.2 V; CMOS; clock skew absorbing flip-flop; delay; energy-delay product improvement; Absorption; Clocks; Delay effects; Flip-flops; Laboratories; Logic; Pulse generation; Switches; Synchronization; Testing;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234326
