Research and Implementation of a Reconfigurable Low Power E0 Algorithm

A low power and dynamic reconfigurable hardware architecture of E0 algorithm is presented, which can satisfy sixteen different LFSRs in the Bluetooth telecommunication systems. The new LFSR design techniques can be also useful in any reconfigurable LFSR. To reduce the conventional switching activity, we proposed the clock-gatiing technique to implement the LFSR. As to the different low power method, the paper performs detailed comparison and analysis. The design has been realized using Altera´s FPGA. Synthesis, placement and routing of reconfigurable design have accomplished on 0.18 mum CMOS process, the result proves Up to 40% power consumption was reduced compared with conventional E0 implementation. And the critical throughput rate can achieve 166 Mbps.