Reduced semiconductor three-level interline dynamic voltage restorer

The previously proposed Interline Dynamic Voltage Restorer (IDVR) system enhances its capability to compensate for long-term and deep voltage sags from propagating to critical loads in power system without requiring a bulky energy storage device. By having multiple DVRs connected to different transmission feeders, the common energy storage in IDVR system can be dynamically replenished from an unaffected feeder so as to maintain the rated power of critical loads in another feeder where voltage sag appears. However, despite its enhancement in compensation capability, the drawbacks faced by original IDVR system are mainly attributed to its complexity in topology and underutilizations of semiconductors. Aimed to improve the system in these aspects, the paper proposes a new IDVR topology with 25% reduction in semiconductors totally used. The theoretical analysis and its operating principles are also presented. In addition, some constraints faced by this new system are also noted. Finally, simulation results are given to validate the feasibility of proposed topology.