Scalability Analysis to Optimize a Network on Chip

New high performance architectures combining high and low level techniques are widely used today, and FPGA-based designs offer excellent platforms for this kind of systems. This paper describes the HIPAOC (high performance architecture on chip) system, a general purpose and reconfigurable high performance architecture implemented on a single FPGA. The proposed design can be configured to work as a shared memory system (multiprocessor) or as a distributed memory system (multicomputer or cluster). The selection of the interconnection network topology in this kind of system is a major design decision. Performance metrics are needed to guide the designer and the user in their decisions with quantitative information. This work proposes a scalability metric and a scalability analysis procedure to optimize the design of networks on chip.