Title :
Scalability Analysis to Optimize a Network on Chip
Author :
Beltran, M. ; Guzman, Armando ; Sevillano, Fernando
Author_Institution :
DATCCCIA, Rey Juan Carlos Univ., Mostoles
Abstract :
New high performance architectures combining high and low level techniques are widely used today, and FPGA-based designs offer excellent platforms for this kind of systems. This paper describes the HIPAOC (high performance architecture on chip) system, a general purpose and reconfigurable high performance architecture implemented on a single FPGA. The proposed design can be configured to work as a shared memory system (multiprocessor) or as a distributed memory system (multicomputer or cluster). The selection of the interconnection network topology in this kind of system is a major design decision. Performance metrics are needed to guide the designer and the user in their decisions with quantitative information. This work proposes a scalability metric and a scalability analysis procedure to optimize the design of networks on chip.
Keywords :
circuit reliability; distributed shared memory systems; field programmable gate arrays; logic design; multiprocessor interconnection networks; network topology; network-on-chip; FPGA-based designs; distributed memory system; high performance architecture on chip system; interconnection network topology; network on chip; scalability analysis; shared memory system; Communication system control; Control systems; Design optimization; Field programmable gate arrays; Hardware; Measurement; Network-on-a-chip; Performance analysis; Scalability; System-on-a-chip;
Conference_Titel :
Advanced Information Networking and Applications, 2009. AINA '09. International Conference on
Conference_Location :
Bradford
Print_ISBN :
978-1-4244-4000-9
Electronic_ISBN :
1550-445X
DOI :
10.1109/AINA.2009.49
