Title :
An algorithm-driven processor design for video compression
Author :
Molloy, Stephen ; Schoner, Brian ; Madisetti, Avanindra ; Jain, Rajeev ; Matic, Roy
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
Abstract :
A design approach for video signal processors is presented that is driven by characteristics of the algorithms, rather than by technological enhancements to conventional microprocessor-style DSP architectures. The goal of this algorithm-driven approach is the design of processors that possess not only the flexibility to execute several algorithms, but an order of magnitude lower complexity than conventional processors. This design approach is applied to the design of a high-speed signal processor targeted at video compression algorithms including the 8×8 DCT, wavelet/subband coding, and vector quantization. The fabricated processor chip can execute each algorithm at up 25 MPixels/sec and has been implemented with only 80,000 transistors in a 1.2-μm CMOS process
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; computational complexity; digital signal processing chips; discrete cosine transforms; transform coding; vector quantisation; video coding; wavelet transforms; 1.2 micron; 1.2-μm CMOS process; 8×8 DCT; algorithm-driven processor design; complexity; high-speed signal processor; subband coding; vector quantization; video compression; video signal processors; wavelet/subband coding; Algorithm design and analysis; CMOS process; Digital signal processing; Discrete cosine transforms; Process design; Signal design; Signal processing; Signal processing algorithms; Vector quantization; Video compression;
Conference_Titel :
Image Processing, 1994. Proceedings. ICIP-94., IEEE International Conference
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-6952-7
DOI :
10.1109/ICIP.1994.413733
