DocumentCode
2108104
Title
A 100 MHz DDS with synchronous oscillator-based phase interpolator
Author
Badets, F. ; Belot, D.
Author_Institution
STMicroelectronics, Crolles, France
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
410
Abstract
A synchronous oscillator-based phase interpolator is used to lower spurious tones of a 100 MHz 16 b DDS. The synchronous oscillator locked-loop produces an eight-phase clock with coarse phase interpolation, while eight identical oscillators coupled with a DAC provide accurate phase adjustment. Spurious tone reduction obtained with the accurate phase interpolation is about 20 dB.
Keywords
BiCMOS digital integrated circuits; Ge-Si alloys; digital-analogue conversion; direct digital synthesis; interpolation; phase locked loops; relaxation oscillators; 0.25 micron; 100 MHz; 100 MHz DDS; 16 bit; BiCMOS SiGe technology; DAC; SiGe; coarse phase interpolation; eight-phase clock; phase adjustment; spurious tone reduction; spurious tones; synchronous oscillator locked-loop; synchronous oscillator-based phase interpolator; Charge pumps; Circuits; Current supplies; Delay; Detectors; Filters; Frequency synchronization; Injection-locked oscillators; Linearity; Phase detection;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234361
Filename
1234361
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