A 700 mW CMOS line driver for ADSL central office applications

Author

Bicakci, A. ; Chun-Sup Kim ; Sang-Soo Lee ; Conroy, C.

Author_Institution

LSI Logic, San Jose, CA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

414

Abstract

A dual-channel analog front-end for ANSI/ETSI standards compliant VDSL in 0.25/0.5/spl mu/m 1P 5M CMOS is presented. The chip includes a non-linearity cancelling multi-path line driver achieving -76dBc 3rd harmonic distortion at 12MHz, a 75mW continuous-time multi-bit 3rd-order self-calibrating /spl Sigma//spl Delta/ ADC, a 14b current-steering DAC with PSD mask post filter, a 0-35dB variable-gain amplifier with adjustable hybrid, and a 12ps jitter LC PLL.

Keywords

CMOS integrated circuits; digital subscriber lines; driver circuits; harmonic distortion; sigma-delta modulation; 0 to 35 dB; 0.25 micron; 0.5 micron; 700 mW; 75 mW; ADSL central office applications; ANSI/ETSI standards compliant VDSL; CMOS; LC PLL; PSD mask post filter; current-steering DAC; dual-channel analog front-end; harmonic distortion; line driver; nonlinearity cancelling multi-path line driver; self-calibrating /spl Sigma//spl Delta/ ADC; variable-gain amplifier; Calibration; Capacitors; Central office; Driver circuits; Operational amplifiers; Power dissipation; Power supplies; Resistors; Schottky diodes; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234363

Filename

1234363