A 700/900mW/channel CMOS dual analog front-end IC for VDSL with integrated 11.5/14.5dBm line drivers

Author

Moyal, M. ; Groepl, M. ; Werker, H. ; Mitteregger, G. ; Schambacher, J.

Author_Institution

Xignal Technol. AG, Munich, Germany

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

416

Abstract

A dual-channel analog front-end for ANSI/ETSI standards compliant VDSL in 0.25/0.5μm 1P 5M CMOS is presented. The chip includes a non-linearity cancelling multi-path line driver achieving -76dBc 3rd harmonic distortion at 12MHz, a 75mW continuous-time multi-bit 3rd-order self-calibrating ΣΔ ADC, a 14b current-steering DAC with PSD mask post filter, a 0-35dB variable-gain amplifier with adjustable hybrid, and a 12ps jitter LC PLL.

Keywords

CMOS analogue integrated circuits; digital subscriber lines; driver circuits; harmonic distortion; sigma-delta modulation; telecommunication standards; 0 to 35 dB; 0.25 micron; 0.5 micron; 12 MHz; 700 mW; 75 mW; 900 mW; ANSI/ETSI standards; CMOS; LC PLL; PSD mask post filter; VDSL; current-steering DAC; dual analog front-end IC; harmonic distortion; line drivers; multi-path line driver; nonlinearity cancelling; self-calibrating /spl Sigma//spl Delta/ ADC; variable-gain amplifier; ANSI standards; Analog integrated circuits; CMOS analog integrated circuits; CMOS integrated circuits; Driver circuits; Filters; Harmonic distortion; Jitter; Phase locked loops; Telecommunication standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234364

Filename

1234364