Title :
Cascaded PLL design for a 90nm CMOS high performance microprocessor
Author :
Wong, K.L. ; Fayneh, E. ; Knoll, E. ; Law, R.H. ; Lim, C.H. ; Parker, R.J. ; Feng Wang ; Cangsang Zhao
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
PLL clock generators are designed for a third-generation NetBurst/spl trade/ processor implemented in a 90nm CMOS process. A cascade configuration offers improved jitter attenuation and facilitates a wide synthesis range. Parameter design takes into account a dual-sloped VCO control. A new charge pump topology offers superior symmetry.
Keywords :
CMOS digital integrated circuits; cascade networks; clocks; microprocessor chips; phase locked loops; 90 nm; CMOS microprocessor; NetBurst processor; cascaded PLL clock generator; charge pump topology; dual-sloped VCO control; jitter attenuation; Capacitors; Clocks; Damping; Filters; Frequency; Jitter; Microprocessors; Phase locked loops; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234366
