Title :
Self-biased, high-bandwidth, low-jitter 1-to-4096 multiplier clock-generator PLL
Author :
Maneatis, J.G. ; Jaeha Kim ; McClatchie, I. ; Maxey, J. ; Shankaradas, M.
Author_Institution :
True Circuits, Los Altos, CA, USA
Abstract :
A self-biased PLL uses a sampled feed-forward filter network and a multi-stage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with < 3.8% period jitter at 1.5V supply. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
Keywords :
CMOS integrated circuits; clocks; current mirrors; feedforward; jitter; multiplying circuits; phase locked loops; programmable circuits; sampled data filters; 0.13 micron; 1.5 V; CMOS chip; constant loop dynamics; multi-stage inverse-linear programmable current mirror; sampled feed-forward filter network; self-biased high-bandwidth low-jitter multiplier clock-generator PLL; Bandwidth; Capacitors; Charge pumps; Charge transfer; Clocks; Filters; Frequency; Jitter; Phase locked loops; Proportional control;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234367
