Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip

Author

Srinivasan, V. ; Liu, K.J.R.

Author_Institution

Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA

Volume

3

fYear

1994

fDate

13-16 Nov. 1994

Firstpage

606

Abstract

Presents a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. The authors show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. The design of the 8×8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2μ CMOS technology.

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; discrete cosine transforms; high definition television; image processing equipment; inverse problems; parallel architectures; pipeline processing; video equipment; video signal processing; 1.2 micron; 1.2μ CMOS technology; 400 Mbit/s; 50 MHz; 8×8 DCT/IDCT; HDTV; design; full custom VLSI implementation; high-speed 2D DCT/IDCT chip; high-speed requirements; inverse DCT; local connectivity; modularity; regularity; scalability; throughput; time-recursive algorithms; CMOS technology; Computer architecture; Discrete cosine transforms; HDTV; Scalability; Throughput; Timing; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing, 1994. Proceedings. ICIP-94., IEEE International Conference

Conference_Location

Austin, TX

Print_ISBN

0-8186-6952-7

Type

conf

DOI

10.1109/ICIP.1994.413734

Filename

413734