Title :
A replica-biased 50% duty cycle PLL architecture with 1/spl times/ VCO
Author :
Kurd, N. ; Griffin, J. ; Barkatullah, J. ; Young, I.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A replica-biased PLL providing wider-frequency-range lower-power consumption and improved clock jitter and loop stability, is fabricated in 0.13/spl mu/m CMOS technology. A wide common-mode input range, matched-current amplifier provides a stable duty cycle at all operating conditions. In comparison of 1/spl times/ and 2/spl times/ VCO architecture, the 1/spl times/ VCO shows improved core timing.
Keywords :
CMOS integrated circuits; clocks; phase locked loops; voltage-controlled oscillators; 0.13 micron; CMOS technology; VCO; clock jitter; common-mode input range; duty cycle; frequency range; loop stability; matched-current amplifier; power consumption; replica-biased PLL architecture; Clocks; Differential amplifiers; Filters; Frequency conversion; Frequency synthesizers; Microprocessors; Phase locked loops; Power supplies; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234368
