A low-power low-jitter adaptive-bandwidth PLL and clock buffer

Author

Mansuri, M. ; Chih-Kong Ken Yang

Author_Institution

California Univ., Los Angeles, CA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

430

Abstract

A multi-context programmable on-chip communication network is implemented using a matrix of Flash-EEPROM pass-transistor switches (FPT) in a 0.18/spl mu/m technology. The prototype 8-context, 8/spl times/8 64b crossbar includes 576k FPT and >8k bi-directional tristate repeaters in an area of 1.38mm/sup 2/. Based on 2/spl times/2 building blocks, wave pipelining and elastic interconnect, data is transferred at 6.4Gb/s per channel, with independent clocks at both ends.

Keywords

buffer circuits; clocks; flash memories; jitter; low-power electronics; phase locked loops; programmable circuits; repeaters; 0.18 micron; 6.4 Gbit/s; Flash-EEPROM pass-transistor switch; bi-directional tristate repeater; clock buffer; crossbar switch; elastic interconnect; low-power low-jitter adaptive-bandwidth PLL; programmable on-chip communication network; wave pipelining; Bidirectional control; Clocks; Communication networks; Communication switching; Network-on-a-chip; Phase locked loops; Pipeline processing; Prototypes; Repeaters; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234370

Filename

1234370