Title :
A delay-line based DCO for multimedia applications using digital standard cells only
Author :
Roth, E. ; Thalmann, M. ; Felber, N. ; Fichtner, W.
Author_Institution :
Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland
Abstract :
A digital clock synthesizer consisting of digital standard cells with 0.5ppm frequency resolution for multimedia applications is implemented in a 0.6/spl mu/m CMOS process. The synthesizer produces an output frequency ranging from 11.1MHz to 12.5MHz with a 100MHz input clock. A DLL-based calibration mechanism tracks PTV variations during operation.
Keywords :
CMOS integrated circuits; delay lines; delay lock loops; frequency synthesizers; voltage-controlled oscillators; 0.6 micron; 100 MHz; 11.1 to 12.5 MHz; CMOS; DLL-based calibration mechanism; PTV variations; delay-line based DCO; digital clock synthesizer; digital standard cells; frequency resolution; multimedia applications; output frequency; Clocks; Delay lines; Digital control; Frequency conversion; Jitter; Multimedia systems; Phase detection; Phase locked loops; Ring oscillators; Streaming media;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234371
