Title :
A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL
Author :
Hsiang-Hui Chang ; Chih-Hao Sun ; Shen-Iuan Liu
Abstract :
The DLL, in 0.35/spl mu/m CMOS, uses the shifted averaging VCDL to reduce the mismatch-induced timing error among the delay stages without extra hardware. The DLL can generate precise multiphase outputs with improved duty cycle, reduced skew errors, and lowered jitter. Compared with a conventional DLL, this design improves the peak-to-peak jitter by a factor of 1.4 at 150MHz.
Keywords :
CMOS integrated circuits; clocks; delay lines; delay lock loops; jitter; 0.35 micron; 150 MHz; CMOS chip; clock generator; duty cycle; mismatch-induced timing error; multiphase delay-locked loop; peak-to-peak jitter; shifted averaging VCDL; skew; Accuracy; Clocks; Delay effects; Hardware; Parasitic capacitance; Power dissipation; Sun; Tail; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234373
