DocumentCode
2108403
Title
A 125MHz 8b digital-to-phase converter
Author
Ju-Ming Chou ; Yu-Tang Hsieh ; Jieh-Tsorng Wu
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
436
Abstract
A digital-to-phase converter (DPC) generates a 125MHz clock with phase shift controlled by an 8b digital input. Averaging resistor rings are used for phase interpolation and phase error reduction by averaging. Implemented in a standard 0.35 /spl mu/m CMOS technology, the DPC achieves /spl plusmn/1 LSB differential nonlinearity and /spl plusmn/2 LSB integral nonlinearity. Power dissipation is 110mW with a 3.3V supply.
Keywords
CMOS integrated circuits; clocks; digital-analogue conversion; interpolation; phase convertors; 0.35 micron; 110 mW; 125 MHz; 3.3 V; 8 bit; CMOS technology; LSB differential nonlinearity; LSB integral nonlinearity; averaging resistor ring; clock generator; digital-to-phase converter; phase error; phase interpolation; power dissipation; Clocks; Delay lines; Digital control; Frequency; Interpolation; Multiplexing; Phase locked loops; Resistors; Ring oscillators; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234374
Filename
1234374
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