Title :
A VLSI architecture for hybrid object-based video motion estimation
Author :
Badawy, Wael ; Bayoumi, Magdy
Author_Institution :
Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA
Abstract :
This paper presents a VLSI architecture that can be used for video object motion estimation. The architecture generates a 2D hierarchical mesh that represents the dynamics of the video object, and it uses a block matching core to generate the motion vectors of the mesh nodes. The architecture uses parallel block matching motion estimation to optimize the latency. Moreover, using the three steps motion estimation algorithm simplifies the motion estimation of the mesh nodes. The architecture has been prototyped and its performance measures have been evaluated. This processor can be used in online object-based video applications such as in MPEG-4, and VRML
Keywords :
CMOS digital integrated circuits; VLSI; data compression; digital signal processing chips; image matching; image representation; motion estimation; video coding; 0.6 mum; 2D hierarchical mesh; CMOS technology; MPEG-4; VLSI architecture; VRML; block matching core; data compression; hierarchical mesh coding; hybrid object-based video motion estimation; latency optimisation; mesh nodes; motion estimation algorithm; motion vectors; online object-based video applications; parallel block matching motion estimation; performance measures; processor; video coding; video object dynamics; video object representation; Computer architecture; Delay; Geometry; MPEG 4 Standard; Mesh generation; Motion estimation; Prototypes; Tracking; Very large scale integration; Video compression;
Conference_Titel :
Electrical and Computer Engineering, 2000 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-5957-7
DOI :
10.1109/CCECE.2000.849635
