Title :
A 2GHz 16dBm IIP3 low noise amplifier in 0.25/spl mu/m CMOS technology
Author :
Yong-Sik Youn ; Jae-Hong Chang ; Kwang-Jin Koh ; Young-Jae Lee ; Hyun-Kyu Yu
Author_Institution :
Electron. & Telecommun. Res. Inst., Daejeon, South Korea
Abstract :
A 2GHz LNA implemented in a 0.25/spl mu/m CMOS technology delivers 14dB gain, 2.8dB NF and 16dBm IIP3. High linearity is obtained by a third-harmonic cancellation technique using a stacked triode structure with differential signals. The method, based on DC non-linear characteristics, improves delay equalization from DC-2GHz with a 17% power increase, 0.8dB gain reduction, and <0.1dB NF increase.
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; differential amplifiers; linearisation techniques; 0.25 micron; 14 dB; 2 GHz; 2.8 dB; CMOS technology; DC nonlinear characteristics; IIP3; delay equalization; differential signal; linearization technique; low-noise amplifier; stacked triode structure; third-harmonic cancellation; CMOS technology; Degradation; FETs; Linearity; Low-noise amplifiers; Noise figure; Semiconductor device noise; Semiconductor optical amplifiers; Topology; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234383
