Title :
A 750MHz 144Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST
Author :
Sakakibara, H. ; Nakayama, M. ; Kusunoki, M. ; Kurita, K. ; Otori, H. ; Hasegawa, M. ; Iwahashi, S. ; Higeta, K. ; Hanashima, T. ; Hayashi, H. ; Kuchimachi, K. ; Uehara, K. ; Nishiyama, T. ; Kume, M. ; Miyamoto, K. ; Kamada, E.
Author_Institution :
Device Dev. Center, Hitachi, Japan
Abstract :
A 750MHz 144Mb cache DRAM LSI incorporates speed-scalable embedded DRAM and SRAM macros, and is realized using a logic-merged DRAM process. The LSI has a built-in at-speed test engine with programmable test pattern and timing, merging logic and memory test. The die area is 285mm/sup 2/ in a 0.18/spl mu/m 6M logic-merged DRAM process.
Keywords :
DRAM chips; built-in self test; cache storage; embedded systems; integrated circuit design; integrated circuit testing; large scale integration; programmable circuits; 0.18 micron; 144 Mbit; 750 MHz; DRAM macro; SRAM macro; cache DRAM LSI; embedded system; logic-merged process; programmable at-speed function-array BIST; speed-scalable design; Built-in self-test; CMOS logic circuits; CMOS technology; Content addressable storage; Delay effects; Frequency; Large scale integration; Random access memory; Scalability; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234385
