DocumentCode
2108683
Title
A 320ps access, 3GHz cycle, 144Kb SRAM macro in 90nm CMOS technology using an all-stage reset control signal generator
Author
Akiyoshi, H. ; Shimizu, H. ; Matsumoto, T. ; Kobayashi, K. ; Sambonsugi, Y.
Author_Institution
Fujitsu, Akiruno, Japan
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
460
Abstract
A 320ps access, 3GHz cycle, 144kb SRAM macro was developed in 90nm CMOS technology. This macro adopts an all-reset control signal generator and hierarchical bit line. These techniques enable both the cycle and access speeds to be 1.7 times faster than those available with 130nm technology.
Keywords
CMOS memory circuits; SRAM chips; macros; signal generators; 144 Kbit; 3 GHz; 320 ps; 90 nm; CMOS technology; SRAM macro; all-stage reset control signal generator; hierarchical bit line; CMOS technology; Latches; Microprocessors; Pulse amplifiers; Pulse circuits; Random access memory; Signal generators; Space vector pulse width modulation; Timing; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234386
Filename
1234386
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