Nonvolatile and SDRAM ferroelectric memories for aerospace applications

A hardened-by-design ferroelectric memory cell has been developed for use in memories hardened to total ionizing dose and single event upset applications. This approach allows for wafer fabrication at commercial ferroelectric semiconductor vendors. To prove this design concept, a test chip has been developed and tested under irradiation. The design on the test chip is a prototype 1-kbit nonvolatile ferroelectric memory. The ferroelectric memory capacitor in the memory cell is intrinsically resistant to radiation exposure. The design also has circuitry for immunity to single event upset (SEU) and latch-up. Based on design simulations, it is possible to develop a similar memory to replace high-speed SDRAM. Nonvolatile and DRAM-like behavior of the memory cell can be controlled by using different internal programming voltages. Lower programming voltages are allow SDRAMs to have higher endurance levels in trade for shorter retention times as compared to the nonvolatile ferroelectric memory. This paper presents the approach used for developing hardened-by-design ferroelectric memory, as well as performance and preliminary radiation hardness results.