Title :
A 1.2 billion operations per second video signal processing chip
Author :
Yates, Rob ; Evans, Stephen ; Ivey, Peter A.
Author_Institution :
Dept. of Electron. & Electr. Eng., Sheffield Univ., UK
Abstract :
Presents a new VLSI processor for image compression and machine vision which combines principles of multi-pipeline and array processing. The device is designed to function as a 2D vector accelerator, as is required for many image coding/processing/vision tasks. The device (DIP chip) is not specific to any one image algorithm, and can be regarded as a general purpose processor. It has variable bit accuracy, variable kernel size and a high input/output bandwidth (greater than 1.2 billion bits per second), and is designed to perform a wide variety of mathematical functions, especially 2D accumulation
Keywords :
CMOS digital integrated circuits; VLSI; computer vision; data compression; digital signal processing chips; image processing equipment; parallel architectures; pipeline processing; reduced instruction set computing; vector processor systems; video coding; 1 micron; 1.2 Gbit/s; 16 bit; 2D accumulation; 2D vector accelerator; DIP chip; VLSI processor; array processing; general purpose processor; image coding; image compression; input bandwidth; machine vision; multi-pipeline processing; output bandwidth; variable bit accuracy; variable kernel size; video signal processing chip; Computer architecture; Convolution; Electronics packaging; Image coding; Image communication; Kernel; Read-write memory; Reduced instruction set computing; Signal processing algorithms; Video signal processing;
Conference_Titel :
Image Processing, 1994. Proceedings. ICIP-94., IEEE International Conference
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-6952-7
DOI :
10.1109/ICIP.1994.413736
