10-GS/s track and hold circuit in 28 nm CMOS

This paper presents the design and characterization of a 10 GS/s track and hold amplifier (THA). The circuit was fabricated in a 28 nm CMOS technology. It is based on a switched capacitor approach. At a sampling rate of 10 GS/s, the total harmonic distortion is -38dBc with a 3.75 GHz input signal. The chip includes an active balun and buffer stages for the clock signal and consumes 50 mW, which is significantly lower than the state-of-the-art at similar performance. It can work with maximum peak-to-peak differential input voltages of up to 800 mV, which is the highest reported for high-speed CMOS implementations and comparable with the performance of state-of-the-art bipolar implementations.