Title :
A low latency architecture for computing multiplicative inverses and divisions in GF(2m)
Author :
Dinh, A.V. ; Palmer, R.J. ; Bolton, R.J. ; Mason, R.
Author_Institution :
TR Labs., Regina Univ., Sask., Canada
Abstract :
A low latency architecture to compute the multiplicative inverse and division in a finite field GF(2m) is presented. Compared to other proposals with the same complexity, this circuit has a lower latency and can be used in error-correction or cryptography to increase the system throughput. This architecture takes advantage of the simplicity to compute powers (2i) of an element in a Galois field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit
Keywords :
Galois fields; VLSI; cryptography; digital arithmetic; error correction; field programmable gate arrays; inverse problems; Galois field; VLSI architecture; complexity; cryptography; divisions; error-correction; finite field; inversion circuit; low latency architecture; multiplication; multiplicative inverses; power calculation; system throughput; Arithmetic; Circuits; Complexity theory; Computer architecture; Delay; Elliptic curve cryptography; Galois fields; Polynomials; Throughput; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 2000 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-5957-7
DOI :
10.1109/CCECE.2000.849667
