High Performance Fast Multiplier

Author

Chaudhary, G.M. ; Kharbash, F.

Author_Institution

Dept. of Comput. Sci. & Electr. Eng., Univ. of Missouri, Kansas City, MO

fYear

2008

fDate

17-20 April 2008

Firstpage

1

Lastpage

4

Abstract

Binary multiplication is very crucial arithmetic operations in digital signal processing systems as well as general computer systems because the performance of the processor is significantly influenced by the speed of their multipliers. In this paper, we present a design-methodology for high-speed multiplications, where two integers of n-bit size each are multiplied to produce a 2n-bit product. This paper presents an efficient method for performing multiplications in one step from the least significant bit towards the most significant bit.

Keywords

digital signal processing chips; arithmetic operations; binary multiplication; computer systems; digital signal processing systems; high performance fast multiplier; high-speed multiplications; Acceleration; Application software; Cities and towns; Computer applications; Computer architecture; Computer science; Digital arithmetic; Digital signal processing; Hardware; High performance computing; High performance fast multiplier; carry-adders; least signifying bet; most significant bit; overflow; partial products; product term; product values;

fLanguage

English

Publisher

ieee

Conference_Titel

Region 5 Conference, 2008 IEEE

Conference_Location

Kansas City, MO

Print_ISBN

978-1-4244-2076-6

Electronic_ISBN

978-1-4244-2077-3

Type

conf

DOI

10.1109/TPSD.2008.4562751

Filename

4562751