Methodology for minimizing power with DSP code

Most research to date on power and energy minimization in DSP processors has focused on hardware solutions. This paper examines the software-based factors affecting power and energy consumption and proposes software techniques by which power and energy can be minimized. Over 150 current measurements were made on a VLIW DSP processor using a rigorous methodology and were used to derive an assembly code based a power prediction model with a mean error of 4.7% and a R² accuracy of 0.93. An assembly code rescheduling algorithm led to improvements in performance and energy consumption of 39% and 32% respectively. This research is important for developing new design methodologies for low power embedded systems, since power is critical to many wireless products in cost sensitive consumer markets