Effect of Loop-Unrolling in Hardware Reconfigurable Implementations of RC5-192 Encryption Algorithm

The objective of this paper is to determine the effects of ´loop-unrolling´ design concept, on the performance of hardware based implementations of the RC5 encryption algorithm. An effort has been done to determine the best value of the number of unrolled loops to implement the RC5 algorithm using 192-bit encryption key. The various models tested were based on single-custom processor with: no-loop-unrolling; loop unrolled implementations with different unrolling sizes. In this research, various performance measures are considered, such as the maximum frequency of operation, circuit size, throughput, and energy consumption. To achieve proper comparison results, all models were developed and mapped to the same hardware reconfigurable chip, a Field Programmable Gate Array (FPGA). The performance parameters of each model were evaluated to determine the best hardware model. Verilog hardware description language was used to model and test all implementations. While no-loop-unrolling provided the least circuit size, the 3-loop-unrolled approach provided the highest throughput, amongst all tested implementations. A throughput speed up of 24% was achieved compared to a reference system implemented in a different target device using a Xilinx FPGA family. Comparing our implementations on the same Altera FPGA family, a maximum throughput speed up of 50% was achieved.