A VLSI architecture for fast computation of third-order cumulants for two-dimensional signals

Higher-order statistics or cumulants, and their associated Fourier transforms, have been established as powerful analytical tools in modern signal processing. To achieve real-time performance in estimating cumulants directly from the incoming time-series data, it is necessary to design a VLSI implementable parallel architecture that speeds up the estimation process. This paper presents a computationally efficient VLSI architecture for computing third-order cumulants for two-dimensional signals. Specifically, the third-order cumulants estimation algorithm is first reformulated so that any redundancy due to symmetry properties is eliminated, and the inherently available parallelism is revealed and exploited by a suitable architecture. It is based on a systolic array implementation and exploits parallelism, pipelining, and regular cell structures. The system architecture consists of (3q²+9q+2) processing elements (PEs), where q is the maximum lag of third-order cumulant sequence. Performance in terms of speedup and efficiency is evaluated