An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC

Author

Sarkar, Santanu ; Banerjee, Swapna

Author_Institution

Dept. of Electron. & Electr. Eng., Indian Inst. of Technol., Kharagpur

fYear

2009

fDate

13-15 May 2009

Firstpage

268

Lastpage

273

Abstract

This paper presents design of an 8-bit 1.8 V segmented current steering (CS) digital-to-analog converter (DAC) using 0.18 mum double poly five metal CMOS technology. The DAC has been segmented as 6+2 to achieve optimum performance for minimum area. The simulation result shows a maximum DNL of 0.30 LSB and an INL of 0.33 LSB. The midcode glitch is 0.27 pV s. The simulated SNDR and SFDR of the segmented DAC are 52.13 dB and 44.83 dB respectively. The settling of the segmented DAC is 6.02 ns. The power consumption is simulated as 7.88 mW. The prototype will be used in telecommunication applications.

Keywords

CMOS integrated circuits; digital-analogue conversion; logic design; current steering; digital-to-analog converter; double poly five metal CMOS technology; power 7.88 mW; power consumption; size 0.18 mum; voltage 0.27 pV; voltage 1.8 V; CMOS process; CMOS technology; Clocks; Computer Society; Decoding; Digital-analog conversion; Energy consumption; Linearity; Prototypes; Very large scale integration; analog CMOS circuits; digital to analog conversion; low power; segmented current steering architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on

Conference_Location

Tampa, FL

Print_ISBN

978-1-4244-4408-3

Electronic_ISBN

978-0-7695-3684-2

Type

conf

DOI

10.1109/ISVLSI.2009.12

Filename

5076419