Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Static NCL

Author

Dugganapally, Indira P. ; Al-Assadi, Waleed K. ; Tammina, Tejaswini ; Smith, Scott

Author_Institution

Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO

fYear

2008

fDate

17-20 April 2008

Firstpage

1

Lastpage

6

Abstract

This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT´s for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and operation mode. The static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.

Keywords

CMOS logic circuits; field programmable gate arrays; logic design; logic gates; table lookup; CMOS; FPGA design; LUT; asynchronous static NULL convention logic library; configurable logic block; logic functions; size 180 nm; static gates; voltage 1.8 V; Circuits; Clocks; Delay; Field programmable gate arrays; Libraries; Logic design; Logic functions; Predictive models; Programmable logic arrays; Table lookup; Configurable Logic Block (CLB); Field Programmable Gate Array (FPGA); Look Up Table (LUT); NULL Convention Logic (NCL);

fLanguage

English

Publisher

ieee

Conference_Titel

Region 5 Conference, 2008 IEEE

Conference_Location

Kansas City, MO

Print_ISBN

978-1-4244-2076-6

Electronic_ISBN

978-1-4244-2077-3

Type

conf

DOI

10.1109/TPSD.2008.4562766

Filename

4562766