The SVT Bypass for a Forward Lepton wide coverage in the CDF Trigger

The silicon-vertex-trigger (SVT) [1,2] at CDF is made of two pipelined processors: the associative-memory, AM [3,4], finding low precision tracks (roads) and the track-fitter, TF, refining the track quality with high-precision fits. We propose to extend the SVT use, now mostly focused on B-physics, to high-P_T physics as a tracker in the forward/backward region. The upgraded SVT structure is easily improved working on firmware, or connecting the existing general purpose FPGA-based SVT boards, named Pulsars, with other Pulsars in a lego-structure. In particular, SVT can easily extend the prompt-lepton acceptance providing silicon-only tracks where the drift-chamber coverage is poor or missing (pseudorapidity larger than 1). Since prompt-leptons from high-P_T events do not require precise impact parameter measurement, we don´t need to measure these tracks with the maximum silicon detector resolution. We enlarge the use of the AM, to detect tracks above a defined P_T threshold. We propose a bypass that brings the new thin roads found by AM, directly to the level-2 CPUs. While the slower full-resolution path (TF) will have to digest the normal AM road production, four new Pulsars will deliver new roads from AM to L2-CPU. All the hardware exists, needs only to be assembled. We present the bypass architecture, the forward-track quality and their possible use in Higgs triggers. The system timing is estimated from simulation on real data and measurements on test stand.