Low Cost and Memoryless CAVLD Architecture for H.264/AVC Decoder

This paper presents a low cost and memoryless hardware design for the context adaptive variable length decoder (CAVLD) of the H.264/AVC video coding standard. Usually, a large number of memory bits and memory accesses are required to decode the CAVLD symbols in H.264/AVC since a great number of syntax elements are decoded based on look-up tables. This is an important problem given the high hardware cost and the high power dissipation caused by the large number of memory accesses. Thus, to solve this problem, we designed an efficient decoding of syntax elements using tree structures. The architecture designed was described in VHDL and synthesized to Altera Stratix II FPGA and to TSMC 0.18 mum standard-cells technologies. The results obtained show that our architecture has significant savings in hardware resources consumption and in the number of memory accesses in comparison to other published works. Our design reached the necessary throughput to decode SDTV videos (720x576 pixels) in real-time.