Title :
Design and Implementation of FPGA Configuration Logic Block Using Asynchronous Semi-Static NCL Circuits
Author :
Dugganapally, Indira P. ; Al-Assadi, Waleed K. ; Pillai, Vijay ; Smith, Scott
Author_Institution :
Dept. of Electr. & Comput. Eng., Missouri Univ. of Sci. & Technol., Rolla, MO
Abstract :
This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT´s for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and Operation mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.
Keywords :
CMOS logic circuits; asynchronous circuits; field programmable gate arrays; integrated circuit modelling; logic design; table lookup; transistors; FPGA configurable logic block design; NCL semistatic gates; TSMC CMOS process; asynchronous semistatic null convention logic library; configuration mode; logic function; look up table; operation mode; semistatic LUT; size 180 nm; transistor level simulation; voltage 1.8 V; Clocks; Delay; Field programmable gate arrays; Hysteresis; Libraries; Logic circuits; Logic design; Programmable logic arrays; Rails; Table lookup; Configurable Logic Block (CLB); Field Programmable Gate Array (FPGA); Look Up Table (LUT); NULL Convention Logic (NCL);
Conference_Titel :
Region 5 Conference, 2008 IEEE
Conference_Location :
Kansas City, MO
Print_ISBN :
978-1-4244-2076-6
Electronic_ISBN :
978-1-4244-2077-3
DOI :
10.1109/TPSD.2008.4562768
