Variation Aware Routing for Three-Dimensional FPGAs

Author

Dong, Chen ; Chilstedt, Scott ; Chen, Deming

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL

fYear

2009

fDate

13-15 May 2009

Firstpage

298

Lastpage

303

Abstract

To maximize the potential of three-dimensional integrated circuit architectures, 3D CAD tools must be developed that are on-par with their 2D counterparts. In this paper, we present a statistical static timing analysis (SSTA) engine designed to deal with both the uncorrelated and correlated variations in 3D FPGAs. We consider the effects of intra-die and inter-die variation. Using the 3D physical design tool TPR as a base, we develop a new 3D routing algorithm which improves the average performance of two layer designs by over 22% and three layer designs by over 27%. To the best of our knowledge, this is the first physical design tool to consider variation in the routing and timing analysis of 3D FPGAs.

Keywords

field programmable gate arrays; logic CAD; network routing; statistical analysis; timing; 3D CAD tools; 3D FPGA; 3D physical design tool; 3D routing algorithm; statistical static timing analysis engine; three-dimensional integrated circuit architecture; variation aware routing; Algorithm design and analysis; Design automation; Engines; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Routing; Stacking; Switches; Timing; 3D Routing; 3D SSTA; Correlated Variation; FPGA; Physical Design; Variation Modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2009. ISVLSI '09. IEEE Computer Society Annual Symposium on

Conference_Location

Tampa, FL

Print_ISBN

978-1-4244-4408-3

Electronic_ISBN

978-0-7695-3684-2

Type

conf

DOI

10.1109/ISVLSI.2009.44

Filename

5076424