A comparative analysis of dual edge triggered flip-flops

Author

Chung, Wai Man ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

Volume

1

fYear

2000

fDate

2000

Firstpage

564

Abstract

A dual edge triggered (DET) flip-flop responds to both edges of the clock. Hence the usage of DET flip-flops reduces clock related power dissipation in digital VLSIs. DET flip-flops are also desirable in high performance applications since the clock frequency can be halved for the same data throughput. We compare several published implementations of DET flip-flops for performance, power consumption. A modified DET flip-flop is proposed that exhibits improved specifications. Preliminary simulations are also carried out to evaluate DET flip-flop sensitivities to VDD, temperature, clock and data rise times, etc

Keywords

VLSI; circuit simulation; clocks; digital integrated circuits; flip-flops; VDD; clock frequency; clock rise time; data rise time; data throughput; digital VLSI; dual edge triggered flip-flops; high performance applications; modified DET flip-flop; power dissipation reduction; simulations; specifications; supply voltage; temperature; Batteries; Capacitance; Clocks; Energy consumption; Flip-flops; Frequency; Power dissipation; Propagation delay; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2000 Canadian Conference on

Conference_Location

Halifax, NS

ISSN

0840-7789

Print_ISBN

0-7803-5957-7

Type

conf

DOI

10.1109/CCECE.2000.849773

Filename

849773