DocumentCode :
2112380
Title :
Employing 65 nm CMOS SOI for 60 GHz WPAN applications
Author :
Mounet, Christopher ; Siligaris, Alexandre ; Michel, Alain ; Capodiferro, Massimo
Author_Institution :
CEA/LETI-MINATEC, Grenoble
fYear :
2008
fDate :
13-14 May 2008
Firstpage :
1
Lastpage :
10
Abstract :
In this paper the design flow of a 60 GHz LNA in a standard CMOS SOI technology is described. First the 60 GHz band opportunities for very high data rate (multi Gbit/sec) wireless communication systems is presented. Then the paper showed the modeling approach for transmission lines as well as for transistors. Passive elements are modeled with the help of HFSS 3D electromagnetic simulator, whilst the transistors use an empirical high frequency oriented CMOS model. A brief description of a 60 GHz transceiver is given.
Keywords :
CMOS integrated circuits; MOSFET; low noise amplifiers; millimetre wave amplifiers; personal area networks; transceivers; transmission lines; CMOS SOI technology; HFSS 3D electromagnetic simulator; LNA design; WPAN application; frequency 60 GHz; passive element; size 65 nm; transceiver; transistor; transmission line; wireless communication system; Analytical models; Bandwidth; CMOS technology; Coplanar waveguides; Electromagnetic modeling; Integrated circuit technology; MMICs; Millimeter wave technology; Personal digital assistants; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microwaves, Communications, Antennas and Electronic Systems, 2008. COMCAS 2008. IEEE International Conference on
Conference_Location :
Tel-Aviv
Print_ISBN :
978-1-4244-2097-1
Electronic_ISBN :
978-1-4244-2098-8
Type :
conf
DOI :
10.1109/COMCAS.2008.4562838
Filename :
4562838
Link To Document :
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