Title :
A Stacked NoC Architecture for Quality-of-Service
Author :
Liu, Yijun ; Li, Zhenkun ; Chen, Pinghua ; Liu, Zhusong
Author_Institution :
Fac. of Comput., Guangdong Univ. of Technol., Guangzhou
Abstract :
As CMOS technology enters sub-micron era, a large number of intelligent properties (IPs) are integrated on a single chip (SoC). The communication patterns become difficult to model. At the same time, as transistors become small and wires become narrow, delays are becoming more and more unpredictable. The factors greatly challenge traditional on-chip buses and point-to-point interconnects because of their problems of scalability and flexibility. In the paper, we propose a stacked on-chip network architecture to provide reliable and efficient on-chip communication in SoCs. The architecture uses a delay-insensitive asynchronous physical channel control scheme and reserved virtual channel control scheme to guarantee the quality-of-service of the on-chip network.
Keywords :
CMOS integrated circuits; asynchronous circuits; integrated circuit design; logic design; network-on-chip; quality of service; CMOS technology; SoC; delay-insensitive asynchronous physical channel control; intelligent property; on-chip communication; quality of service; reserved virtual channel control; stacked NoC architecture; stacked on-chip network architecture; asynchronous logic; on-chip network; quality-of-service; stacket architecture;
Conference_Titel :
Information Science and Engineering, 2008. ISISE '08. International Symposium on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-2727-4
DOI :
10.1109/ISISE.2008.241