Hardware implementation of a general multi-way jump mechanism

A VLIW architecture capable of testing multiple conditions in one cycle must support effective multiway (conditional) jumps. In this paper, a hardware-implemented, fast, and space-efficient multi-way jump mechanism is developed that speeds up the execution of multiple conditional jumps and reduces wasted storage. A cluster of multiple conditional jumps packed in an instruction can form an arbitrary rooted DAG (directed acyclic graph), where each node corresponds to a condition. The authors scheme provides a hardware device called an M-unit, which can combinationally produce the next target address using an encoded description of the DAG and the actual test bits. A technique to reduce the number of different configurations is introduced, along with a memory packing scheme that minimizes wasted memory