Title :
A new hybrid low-latency serial-parallel multiplier
Author :
Al-Besher, B. ; Bouridane, A. ; Ashur, A.S. ; Crookes, D.
Author_Institution :
Dept. of Comput. Sci., Queen´´s Univ., Belfast, UK
fDate :
31 May-3 Jun 1998
Abstract :
A new low latency most significant bit first (MSBF), hybrid multiplier architecture is presented in this paper. This multiplier architecture requires fewer pipelining latches than the existing multiplier architectures and reduces the clock-speed for every cycle in the multiplication process. Furthermore, compared with previous MSBF multipliers the initial delay (latency) is also reduced to three cycles, and one 2n-digit product is produced every 2n+3 cycles
Keywords :
clocks; delays; multiplying circuits; clock-speed; hybrid low-latency serial-parallel multiplier; initial delay; most significant bit first multiplier; multiplication process; pipelining latches; Arithmetic; Clocks; Computer architecture; Computer science; Convolution; Delay; Image coding; Image processing; Pipeline processing; Signal processing;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.694448
