Design for Reliability of Wafer Level Packages

Wafer level packages are one of the most advanced packaging concepts. It combines the advantages of flip chip with conventional surface mount technologies. In recent years we have seen a tremendous growth in the application of wafer level packages, both in quantities as well as in the number of products where they are implemented. The technology is, however, not without it´s challenges with 1st and 2nd level reliability issues. For instance, the limit on the size of wafer level packages has to do with the 2nd level, or solder bump, reliability. This paper highlights our major research and development results on understanding and enhancing the 1st and 2nd level reliability of wafer level packages using combined experimental and virtual prototyping (thermal, mechanical and thermo-mechanical) techniques. Typical 1st level reliability problems within wafer level packages are cracking of repassivation materials, fatigue of bond over active pads, and cracks within the under bump metallisation. To investigate the physics of failure for these problems, dedicated parametric finite element models are constructed including the thin IC layers. Different repassivation materials and different structures are explored to their potential reliability benefits. By combining the experimental results with reliability prediction models and advanced simulation-based optimisation methods, the complete wafer level package design space in terms of distance from neutral point, PCB thickness, PCB copper layout, and use of improved structures is explored. Our numerical results explain the experimentally obtained reliability results for the effects of package size and PCB thickness. Even more, they indicate that by properly designing the copper layout in the PCB, a 10-20% improvement can be achieved for the WLP 2nd level reliability