Inductor optimization procedure for Power Supply in Package and Power Supply on Chip

For Voltage Regulator Modules (VRM), integrating the power converter with the load in an advanced integration process is a method to deliver power at higher voltage levels, and thereby overcome the high supply current requirements predicted by the 2009 International Technology Roadmap for Semiconductors (ITRS). The most conventional converter type used is the buck or step-down converter. For this converter, the output inductor is recognized as the performance limiting component with respect to efficiency and area requirements. This paper details an inductor optimization procedure for Power Supply in Package (PSiP) and Power Supply on Chip (PwrSoC) applications. Targeting the highest possible efficiency for a specified area-related power density, the optimization procedure determines the best inductor dimensions given the buck converter operating conditions. The optimization procedure is verified using experimental data obtained from a PCB inductor realization. According to the results, the most favorable inductor achieves an efficiency of 94.5% and an area-related power density of 1.97W/mm² at a switching frequency of 170MHz.