Mismatch reduction for dark current suppression

In this paper we present a dark current suppression technique for low-light image sensor arrays fabricated in a standard CMOS process. It has been shown that reducing the reverse bias of a p-n junction minimizes the thermally generated dark current and increases the signal to noise ratio. While this work well for single sensors, arrays of sensors suffer from mismatch, which limits the ability to apply a consistent junction bias. In this work we show simulation results for a floating gate mismatch compensation technique which reduces this biasing mismatch. While simulations of an idealized structure provided a 40X reduction in mismatch compensation, a worst case simulation provided only a 6X reduction in mismatch. For the idealized simulation, the standard deviation of the input referred mismatch was reduced from 7.7 mV to 196 μV, while in the worst case simulation the standard deviation of the input referred mismatch was reduced to 1.4 mV, corresponding to an approximate dark current reduction of 10X and 5X respectively.