Title :
Virtual Prototyping based Design Optimization of the Substrate, Leadframe, and Flip Chip Package Families with Low-k Technology
Author :
van Driel, W.D. ; Grech, A.-M. ; Hauck, T. ; Schmadlak, I. ; Zhang, X. ; Orain, S.
Author_Institution :
Philips Semicond., Nijmegen
Abstract :
The continuous industry drive for miniaturization and function integration forces the development of feature sizes down to the nanometer regime. Although the industry has just solved the major problems in CMOS090 technology, a new hurdle is to be taken: CMOS065. And again, new materials will be introduced. Black Diamond-I, used in CMOS090, will be replaced by Black Diamond-II(x). This new material is porous and, thus, not being a homogeneous material any more. For sure that this will have major impacts on the thermomechanical performance of the total IC stack. The problems encountered during CMOS090 at least showed that IC and package reliability (and PCB?) are strongly interacted. Finite element techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes and/or product testing. Modeling techniques such as contact elements, global-local, sub-structuring, element birth and death and material models such as fracture mechanics, visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic package. Still, experiments are necessary to verify the calculated results in order to be sure that the results obtained from FE models are reliable and accurate enough from both quantitative and qualitative perspective. No doubt that to first-time-right develop CMOS065 and beyond will require the use of combined state-of-the-art modeling and experimental techniques. It will enable the industry not only to predict thermo-mechanically induced failures in electronic packages in early stages, but also to understand the precise failure mechanisms involved. To strengthen the development, the Crolles2 Alliance was founded between the industry leaders STMicroelectronics, Philips, and Freescale. As part of the Alliance, the CAA Modeling Cooperation, consisting of the representatives of each companies modeling team started to assist the 65-node development - - with state-of-the-art virtual prototyping techniques. This paper highlights the major research and development results of that cooperation so far
Keywords :
CMOS integrated circuits; circuit optimisation; flip-chip devices; integrated circuit design; integrated circuit manufacture; integrated circuit modelling; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; low-k dielectric thin films; substrates; virtual prototyping; Black Diamond-I; Black Diamond-II(x); CMOS065; CMOS090; deformations; design optimization; electronic package; failure mechanisms; finite element techniques; flip chip package; integrated circuit; leadframe; low-k technology; package reliability; packaging manufacturing processes; product testing; stresses; substrate; thermomechanical performance; virtual prototyping techniques; CMOS integrated circuits; CMOS technology; Design optimization; Electronic packaging thermal management; Finite element methods; Flip chip; Integrated circuit packaging; Predictive models; Thermomechanical processes; Virtual prototyping;
Conference_Titel :
Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006. EuroSime 2006. 7th International Conference on
Conference_Location :
Como
Print_ISBN :
1-4244-0275-1
DOI :
10.1109/ESIME.2006.1644013