Design consideration of 0.4V-operation SOTB MOSFET for super low power application

The silicon on thin buried oxide (SOTB) CMOS is suited for ultralow-voltage operation of CMOS circuits, that is required for drastic power reduction of LSIs because of its small variability and adaptive back bias controllability. In this study, we show that the design concept of threshold voltage for ultralow-voltage (V_dd=0.4V) operation of SOTB. To achieve a good trade-off of I_on and I_off, gate work function (Φ_WF) should be controlled at 4.25-4.35eV and 4.90-5.05eV for N- and P-type MOS-FETs (NMOS and PMOS), respectively. Moreover, higher N_sub is preferable for increasing I_on. Our optimized design achieved that I_on values 170 and 89 μA/μm at I_off values of 5.6 and 7.8 pA/μm for NMOS and PMOS, respectively. This result indicates that the 0.4-v operation is possible without paying significant speed penalty from the conventional 1-V operation.