An efficient design methodology for standard cell circuits

A novel standard cell design methodology is presented that is based on the implementation of interconnections over the gates to avoid dedicated connection channels. A priority scheme is used for the allocation of the metal layer. The result is a very compact layout. A standard cell library was designed using a double-metal CMOS technology. The topological structure and cell library are presented. The development of a software tool to compile integrated circuits using the available cells is also discussed, and the placement and routing strategies used in the implementation algorithm are described.<>