Reliability Optimization of Stacked System-in-Package Using FEA

Author

Valtanen, Jani ; Heino, Pekka

Author_Institution

Inst. of Electron., Tampere Univ. of Technol.

fYear

2006

fDate

24-26 April 2006

Firstpage

1

Lastpage

5

Abstract

In this work, thermo-mechanical reliability of solder joints of stacked thinned bare dice system-in-package is studied with the finite element method using three-dimensional models. The studied package consists of one to five layers. In every layer two 5 mm times 5 mm silicon chips have been joined with flip chip method onto an 8 mm times 14 mm aramid-epoxy or FR-4 interposer. The package has been simulated varying the number of layers, the thicknesses of interposers and silicon chips, interposer material. Moreover, the package with three layers is studied for component placement optimization. Different sized components are used to find optimal layer structure depending on their size. The results show that every studied aspect has effect on the reliability of stacked system-in-package and with good design it is possible to increase the life time of the package

Keywords

finite element analysis; flip-chip devices; integrated circuit reliability; silicon; solders; system-in-package; 14 mm; 3D models; 5 mm; 8 mm; FR-4 interposer; Si; component placement optimization; finite element analysis; finite element method; flip chip method; interposer material; silicon chips; solder joints; stacked system-in-package; thermo-mechanical reliability; Creep; Electronics packaging; Flip chip; Materials reliability; Optical sensors; Silicon; Soldering; Temperature; Thermal resistance; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006. EuroSime 2006. 7th International Conference on

Conference_Location

Como

Print_ISBN

1-4244-0275-1

Type

conf

DOI

10.1109/ESIME.2006.1644049

Filename

1644049