Title :
Fast FEC synchronization for 10G Ethernet receiver
Author :
Yang, Hao ; Yan, Xiaolang
Author_Institution :
Institute of VLSI Design, Zhejiang University, Hangzhou, China
Abstract :
The synchronization duration is longer in 10G Ethernet application compare with previous ones due to higher performance and reliability requirement. In worse case, a 2112-bit FEC block in 10G/40G/100G Ethernet applications needs around 9 million bit cycles to achieve synchronized status. This paper introduces a faster method to synchronize the FEC block. Add a smart shift to drop less frame bits and re-use FEC decoder components can help to reduce the synchronization time to 26% compare with traditional way.
Keywords :
Decoding; Ethernet networks; Forward error correction; Generators; Hardware; Receivers; Synchronization; 10G/40G/100G Ethernet; Bit Shift; Block Synchronization; FEC(Forward Error Correction);
Conference_Titel :
Information Science and Engineering (ICISE), 2010 2nd International Conference on
Conference_Location :
Hangzhou, China
Print_ISBN :
978-1-4244-7616-9
DOI :
10.1109/ICISE.2010.5690024
