A novel SEPIC-derived PFC pre-regulator without electrolytic capacitor for PWM dimming LED lighting application based on valley fill circuit

High brightness white LED has attracted a lot of attention for its high efficacy, simple to drive, environmentally friendly, long lifespan and small size. The power supply for LED also requires long life while maintaining high efficiency, high power factor and low cost. However, a typical design employs electrolytic capacitor as storage capacitor, which is not only bulky, but also with short lifespan, thus hampering the entire LED lighting system. In this paper, a novel PFC topology is proposed by inserting the valley fill circuit in the SEPIC-derived converter, which can reduce the voltage stress of storage capacitor and output diode to half under the same power factor condition. This valley fill SEPIC-derived PFC topology is then proposed for LED lighting application. By allowing a relatively large voltage ripple allowable in a PFC design and operating in DCM, the proposal is able to eliminate the electrolytic capacitor while maintaining high power factor. The basic operating principle and analysis will be described in detail. A 50-W prototype has been built to verify the proposed approach.